summary of the invention Accordingly
, the present invention is direct to ESD protection circuits and Methods That obviate one or more of the Problems due to Limitations and Disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the circuits and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp having at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.
In one aspect of the present invention, the CDM clamp is an n-type active device having one of low, zero, or negative threshold voltage.
In another aspect of the present invention, the CDM clamp is a p-type active device having one of low, zero, or positive threshold voltage.
Also in accordance with the present invention, there is provided an integrated circuit that includes a first voltage line, a second voltage line, a transistor having a gate coupled to the first voltage line and a substrate coupled to the second voltage line, and a CDM clamp coupled between the gate and the substrate of the transistor, the CDM clamp including at least one active device having a low threshold voltage, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to one of the first voltage line or second voltage line during an ESD event.
Further in accordance with the present invention, there is provided an integrated circuit that includes a contact pad a transistor having a substrate, a CDM protection circuit comprising a CDM clamp coupled between the contact pad and the substrate of the transistor, the CDM clamp including at least one active device, and an HBM/MM protection circuit disposed between the contact pad and the CDM protection circuit comprising at least one HBM/MM clamp coupled to the contact pad, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad as the contact pad is grounded.
Still in accordance with the present invention, there is provided a method for providing electrostatic discharge protection that includes providing a contact pad, grounding the contact pad, providing a transistor having a substrate, providing an active device CDM clamp coupled between the contact pad and the substrate of the transistor, accumulating electrostatic charges in the substrate of the transistor, and conducting the accumulated electrostatic charges in the substrate of the transistor to the contact pad.
Yet still in accordance with the present invention, there is provided a method for providing electrostatic discharge protection that includes providing a contact pad, providing a transistor having a substrate, providing a CDM protection circuit including a CDM clamp coupled between the contact pad and the substrate of the transistor, the CDM clamp having at least one active device, providing an HBM/MM protection circuit disposed between the contact pad and the CDM protection circuit comprising at least one HBM/MM clamp coupled to the contact pad, and conducting electrostatic charges accumulated in the substrate of the transistor to the contact pad as the contact pad is grounded.
It is to Be Understood That Both the foregoing general description and the Following Are Exemplary Detailed description and explanatory and Are Intended to Provide Further Explanation of the invention as claim.
Luis Fernando Cantor Well
19135529
Engineering Solid state electronics electonica
Section 2
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