DESCRIPTION OF THE Embodiment
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
An active device generally refers to a metal-oxide-semiconductor ("MOS") transistor that is able to quickly turn on, or is "initial-on" to conduct an ESD current during an ESD event. The active device has a lightly-doped region formed between a source and a drain region of the transistor and therefore has a low threshold voltage, specifically, a zero or negative threshold voltage for n-type active devices, and a zero or positive threshold voltage for p-type active devices. An n-type active device refers to an electrostatic discharge protection device comprising a p-type substrate, an n-type source region, an n-type drain region, a gate, and a lightly doped p-type region formed between the source and drain regions and under the gate. A negative voltage, i.e., smaller than V SS , is needed to turn off the n-type active device. A p-type active device refers to an electrostatic discharge protection device comprising an n-type substrate, an p-type source region, an p-type drain region, a gate, and a lightly doped n-type region formed between the source and drain regions and under the gate. A positive voltage greater V DD , is needed to turn off the p-type active device.
The active devices have the advantages of being able to quickly respond to an ESD event with strong ESD robustness. Additional details about active devices are discussed in the related U.S. patent application to Ker et al, U.S. patent application Ser. No. 10/230,055, entitled "ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF MANUFACTURING THE SAME," filed on Aug. 29, 2002.
The present invention therefore also provides a method for electrostatic discharge protection. In one embodiment, the method includes providing a CDM clamp coupled between a contact pad and a substrate of a transistor, in which the CDM clamp includes at least one active device, and conducting electrostatic charges accumulated in the substrate of the transistor to the contact pad as the contact pad is grounded.
In another embodiment, the method includes providing a CDM protection circuit comprising a CDM clamp coupled between a contact pad and a substrate of a transistor, in which the CDM clamp is an active device, providing an HBM/MM protection circuit disposed between the contact pad and the CDM protection circuit comprising at least one HBM/MM clamp coupled to the contact pad, and conducting electrostatic charges accumulated in the substrate of the transistor to the contact pad as the contact pad is grounded.
In still another embodiment, the method includes providing a transistor having a gate coupled to a first voltage line, and a substrate coupled to a second voltage line, providing a CDM clamp coupled between the gate and substrate of the transistor, and conducting electrostatic charges accumulated in the substrate of the transistor to one of the first or second voltage line during an ESD event.
It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention Disclosed HEREIN. It is Intended That the specification and examples as Exemplary BE considers only, with a true scope and spirit of the invention Being Indicated by the Following Claims.
Luis Fernando Cantor Well
19135529
Engineering Solid State Electronics
Section 2
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